From 36686d8f1a9447ded5bdb204df12b2551009030e Mon Sep 17 00:00:00 2001 From: Tony Yang Date: Sun, 28 Nov 2021 22:30:44 +0800 Subject: [PATCH] [Feature] show scan code on 7-segment --- Keyboard Sample Code/KeyboardConstraints.xdc | 4 +- Keyboard Sample Code/SampleDisplay.v | 105 ++++----------- Keyboard Sample Code/SevenSegment.v | 132 ++++++++++--------- 3 files changed, 99 insertions(+), 142 deletions(-) diff --git a/Keyboard Sample Code/KeyboardConstraints.xdc b/Keyboard Sample Code/KeyboardConstraints.xdc index 6f9d5d3..4fcab17 100755 --- a/Keyboard Sample Code/KeyboardConstraints.xdc +++ b/Keyboard Sample Code/KeyboardConstraints.xdc @@ -19,8 +19,8 @@ set_property PACKAGE_PIN V5 [get_ports {display[5]}] set_property PACKAGE_PIN U7 [get_ports {display[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {display[6]}] -#set_property PACKAGE_PIN V7 [get_ports dp] - #set_property IOSTANDARD LVCMOS33 [get_ports dp] +# set_property PACKAGE_PIN V7 [get_ports dp] +# set_property IOSTANDARD LVCMOS33 [get_ports dp] set_property PACKAGE_PIN U2 [get_ports {digit[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {digit[0]}] diff --git a/Keyboard Sample Code/SampleDisplay.v b/Keyboard Sample Code/SampleDisplay.v index 338fcae..dbbed74 100755 --- a/Keyboard Sample Code/SampleDisplay.v +++ b/Keyboard Sample Code/SampleDisplay.v @@ -5,49 +5,27 @@ module SampleDisplay( inout wire PS2_CLK, input wire rst, input wire clk - ); - - parameter [8:0] LEFT_SHIFT_CODES = 9'b0_0001_0010; - parameter [8:0] RIGHT_SHIFT_CODES = 9'b0_0101_1001; - parameter [8:0] KEY_CODES_00 = 9'b0_0100_0101; // 0 => 45 - parameter [8:0] KEY_CODES_01 = 9'b0_0001_0110; // 1 => 16 - parameter [8:0] KEY_CODES_02 = 9'b0_0001_1110; // 2 => 1E - parameter [8:0] KEY_CODES_03 = 9'b0_0010_0110; // 3 => 26 - parameter [8:0] KEY_CODES_04 = 9'b0_0010_0101; // 4 => 25 - parameter [8:0] KEY_CODES_05 = 9'b0_0010_1110; // 5 => 2E - parameter [8:0] KEY_CODES_06 = 9'b0_0011_0110; // 6 => 36 - parameter [8:0] KEY_CODES_07 = 9'b0_0011_1101; // 7 => 3D - parameter [8:0] KEY_CODES_08 = 9'b0_0011_1110; // 8 => 3E - parameter [8:0] KEY_CODES_09 = 9'b0_0100_0110; // 9 => 46 - - parameter [8:0] KEY_CODES_10 = 9'b0_0111_0000; // right_0 => 70 - parameter [8:0] KEY_CODES_11 = 9'b0_0110_1001; // right_1 => 69 - parameter [8:0] KEY_CODES_12 = 9'b0_0111_0010; // right_2 => 72 - parameter [8:0] KEY_CODES_13 = 9'b0_0111_1010; // right_3 => 7A - parameter [8:0] KEY_CODES_14 = 9'b0_0110_1011; // right_4 => 6B - parameter [8:0] KEY_CODES_15 = 9'b0_0111_0011; // right_5 => 73 - parameter [8:0] KEY_CODES_16 = 9'b0_0111_0100; // right_6 => 74 - parameter [8:0] KEY_CODES_17 = 9'b0_0110_1100; // right_7 => 6C - parameter [8:0] KEY_CODES_18 = 9'b0_0111_0101; // right_8 => 75 - parameter [8:0] KEY_CODES_19 = 9'b0_0111_1101; // right_9 => 7D - - reg [15:0] nums, next_nums; - reg [3:0] key_num; - reg [9:0] last_key; - - wire shift_down; +); + wire reset; + + reg [7:0] scan_code, nxt_scan_code; + wire [511:0] key_down; wire [8:0] last_change; wire been_ready; - - assign shift_down = (key_down[LEFT_SHIFT_CODES] == 1'b1 || key_down[RIGHT_SHIFT_CODES] == 1'b1) ? 1'b1 : 1'b0; - - SevenSegment seven_seg ( - .display(display), - .digit(digit), - .nums(nums), - .rst(rst), - .clk(clk) + + OnePulse one_pulse( + .signal_single_pulse(reset), + .signal(rst), + .clock(clk) + ); + + SegmentController controller ( + .clk(clk), + .rst_n(!reset), + .signal({(last_change[8] ? 8'hE0 : 8'd0), scan_code}), + .seg(display), + .seg_an(digit) ); KeyboardDecoder key_de ( @@ -56,54 +34,21 @@ module SampleDisplay( .key_valid(been_ready), .PS2_DATA(PS2_DATA), .PS2_CLK(PS2_CLK), - .rst(rst), + .rst(reset), .clk(clk) ); - always @ (posedge clk, posedge rst) begin - if (rst) begin - nums <= 16'b0; + always @ (posedge clk, posedge reset) begin + if (reset) begin + scan_code <= 16'd0; end else begin - nums <= next_nums; + scan_code <= nxt_scan_code; end end - always @ (*) begin - next_nums = nums; - if (been_ready && key_down[last_change] == 1'b1) begin - if (key_num != 4'b1111) begin - if (shift_down == 1'b1) begin - next_nums = {key_num, nums[15:4]}; - end else begin - next_nums = {nums[11:0], key_num}; - end - end else next_nums = next_nums; - end else next_nums = next_nums; - end always @ (*) begin - case (last_change) - KEY_CODES_00 : key_num = 4'b0000; - KEY_CODES_01 : key_num = 4'b0001; - KEY_CODES_02 : key_num = 4'b0010; - KEY_CODES_03 : key_num = 4'b0011; - KEY_CODES_04 : key_num = 4'b0100; - KEY_CODES_05 : key_num = 4'b0101; - KEY_CODES_06 : key_num = 4'b0110; - KEY_CODES_07 : key_num = 4'b0111; - KEY_CODES_08 : key_num = 4'b1000; - KEY_CODES_09 : key_num = 4'b1001; - KEY_CODES_10 : key_num = 4'b0000; - KEY_CODES_11 : key_num = 4'b0001; - KEY_CODES_12 : key_num = 4'b0010; - KEY_CODES_13 : key_num = 4'b0011; - KEY_CODES_14 : key_num = 4'b0100; - KEY_CODES_15 : key_num = 4'b0101; - KEY_CODES_16 : key_num = 4'b0110; - KEY_CODES_17 : key_num = 4'b0111; - KEY_CODES_18 : key_num = 4'b1000; - KEY_CODES_19 : key_num = 4'b1001; - default : key_num = 4'b1111; - endcase + if (been_ready && key_down[last_change] == 1'b1) nxt_scan_code = last_change[7:0]; + else nxt_scan_code = scan_code; end endmodule diff --git a/Keyboard Sample Code/SevenSegment.v b/Keyboard Sample Code/SevenSegment.v index 753bf36..8268176 100755 --- a/Keyboard Sample Code/SevenSegment.v +++ b/Keyboard Sample Code/SevenSegment.v @@ -1,69 +1,81 @@ -module SevenSegment( - output reg [6:0] display, - output reg [3:0] digit, - input wire [15:0] nums, - input wire rst, - input wire clk - ); - - reg [15:0] clk_divider; - reg [3:0] display_num; - - always @ (posedge clk, posedge rst) begin - if (rst) begin - clk_divider <= 16'b0; +module ClockDivider #( + parameter N = 20 +) ( + input clk, + input rst_n, + output reg dclk +); + reg [N-1:0] dff; + always @(posedge clk) begin + if (!rst_n) begin + dff <= {N{1'b0}}; end else begin - clk_divider <= clk_divider + 16'b1; + dff <= dff + 1'b1; + dclk <= &dff; end end - - always @ (posedge clk, posedge rst) begin - if (rst) begin - display_num <= 4'b0000; - digit <= 4'b1111; - end else if (clk_divider == {16{1'b1}}) begin - case (digit) - 4'b1110 : begin - display_num <= nums[7:4]; - digit <= 4'b1101; - end - 4'b1101 : begin - display_num <= nums[11:8]; - digit <= 4'b1011; - end - 4'b1011 : begin - display_num <= nums[15:12]; - digit <= 4'b0111; - end - 4'b0111 : begin - display_num <= nums[3:0]; - digit <= 4'b1110; - end - default : begin - display_num <= nums[3:0]; - digit <= 4'b1110; - end - endcase +endmodule + +module SegmentController ( + input clk, + input rst_n, + input [15:0] signal, + output [6:0] seg, + output [3:0] seg_an +); + wire dclk; + wire [3:0] seg_en; + + reg [1:0] cnt; + + reg [6:0] seg_inv; + reg [3:0] digit; + + ClockDivider #(.N(16)) display(clk, rst_n, dclk); + + always @(posedge clk) begin + if (!rst_n) begin + cnt <= 4'd0; + end else if (dclk) begin + cnt <= cnt + 1'b1; end else begin - display_num <= display_num; - digit <= digit; + cnt <= cnt; end end - - always @ (*) begin - case (display_num) - 0 : display = 7'b1000000; //0000 - 1 : display = 7'b1111001; //0001 - 2 : display = 7'b0100100; //0010 - 3 : display = 7'b0110000; //0011 - 4 : display = 7'b0011001; //0100 - 5 : display = 7'b0010010; //0101 - 6 : display = 7'b0000010; //0110 - 7 : display = 7'b1111000; //0111 - 8 : display = 7'b0000000; //1000 - 9 : display = 7'b0010000; //1001 - default : display = 7'b1111111; + + always @(*) begin + case (cnt) + 2'd0: digit = signal[3:0]; + 2'd1: digit = signal[7:4]; + 2'd2: digit = signal[11:8]; + 2'd3: digit = signal[15:12]; + default: digit = 4'd0; endcase end - + + always @(*) begin + case (digit) + 4'h0: seg_inv = 7'b0111111; + 4'h1: seg_inv = 7'b0000110; + 4'h2: seg_inv = 7'b1011011; + 4'h3: seg_inv = 7'b1001111; + 4'h4: seg_inv = 7'b1100110; + 4'h5: seg_inv = 7'b1101101; + 4'h6: seg_inv = 7'b1111101; + 4'h7: seg_inv = 7'b0000111; + 4'h8: seg_inv = 7'b1111111; + 4'h9: seg_inv = 7'b1101111; + 4'ha: seg_inv = 7'b1110111; + 4'hb: seg_inv = 7'b1111100; + 4'hc: seg_inv = 7'b0111001; + 4'hd: seg_inv = 7'b1011110; + 4'he: seg_inv = 7'b1111001; + 4'hf: seg_inv = 7'b1110001; + default: seg_inv = 7'b0000000; + endcase + end + + assign seg = ~seg_inv; + assign seg_en = {(signal[15:8] == 8'hE0 ? 2'b11 : 2'b00), 2'b11}; + assign seg_an = ~(seg_en & (4'b1 << cnt)); endmodule