t510599/keyboard-sample
0
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix dclk as DFF trigger clock

Browse Source
This commit is contained in:
Samuel Huang 2021-11-26 18:16:05 +08:00
parent dd4aa79cfd
commit c2c8ec302e
1 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
Keyboard Sample Code/SevenSegment.v
View File

@ -11,17 +11,17 @@ module SevenSegment(
always @ (posedge clk, posedge rst) begin
if (rst) begin
clk_divider <= 15'b0;
clk_divider <= 16'b0;
end else begin
clk_divider <= clk_divider + 15'b1;
clk_divider <= clk_divider + 16'b1;
end
end
always @ (posedge clk_divider[15], posedge rst) begin
always @ (posedge clk, posedge rst) begin
if (rst) begin
display_num <= 4'b0000;
digit <= 4'b1111;
end else begin
end else if (clk_divider == {16{1'b1}}) begin
case (digit)
4'b1110 : begin
display_num <= nums[7:4];
@ -44,6 +44,9 @@ module SevenSegment(
digit <= 4'b1110;
end
endcase
end else begin
display_num <= display_num;
digit <= digit;
end
end