module ClockDivider #(
    parameter N = 20
) (
    input clk,
    input rst_n,
    output reg dclk
);
    reg [N-1:0] dff;
    always @(posedge clk) begin
        if (!rst_n) begin
            dff <= {N{1'b0}};
        end else begin
            dff <= dff + 1'b1;
            dclk <= &dff;
        end
    end
endmodule

module SegmentController (
    input clk,
    input rst_n,
    input [15:0] signal,
    output [6:0] seg,
    output [3:0] seg_an
);
    wire dclk;
    wire [3:0] seg_en;

    reg [1:0] cnt;

    reg [6:0] seg_inv;
    reg [3:0] digit;

    ClockDivider #(.N(16)) display(clk, rst_n, dclk);

    always @(posedge clk) begin
        if (!rst_n) begin
            cnt <= 4'd0;
        end else if (dclk) begin
            cnt <= cnt + 1'b1;
        end else begin
            cnt <= cnt; 
        end
    end

    always @(*) begin
        case (cnt)
            2'd0: digit = signal[3:0];
            2'd1: digit = signal[7:4];
            2'd2: digit = signal[11:8];
            2'd3: digit = signal[15:12];
            default: digit = 4'd0;
        endcase
    end

    always @(*) begin
        case (digit)
            4'h0: seg_inv = 7'b0111111;
            4'h1: seg_inv = 7'b0000110;
            4'h2: seg_inv = 7'b1011011;
            4'h3: seg_inv = 7'b1001111;
            4'h4: seg_inv = 7'b1100110;
            4'h5: seg_inv = 7'b1101101;
            4'h6: seg_inv = 7'b1111101;
            4'h7: seg_inv = 7'b0000111;
            4'h8: seg_inv = 7'b1111111;
            4'h9: seg_inv = 7'b1101111;
            4'ha: seg_inv = 7'b1110111;
            4'hb: seg_inv = 7'b1111100;
            4'hc: seg_inv = 7'b0111001;
            4'hd: seg_inv = 7'b1011110;
            4'he: seg_inv = 7'b1111001;
            4'hf: seg_inv = 7'b1110001;
            default: seg_inv = 7'b0000000;
        endcase
    end

    assign seg = ~seg_inv;
    assign seg_en = {(signal[15:8] == 8'hE0 ? 2'b11 : 2'b00), 2'b11};
    assign seg_an = ~(seg_en & (4'b1 << cnt));
endmodule