82 lines
1.9 KiB
Verilog
Executable File
82 lines
1.9 KiB
Verilog
Executable File
module ClockDivider #(
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parameter N = 20
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) (
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input clk,
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input rst_n,
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output reg dclk
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);
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reg [N-1:0] dff;
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always @(posedge clk) begin
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if (!rst_n) begin
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dff <= {N{1'b0}};
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end else begin
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dff <= dff + 1'b1;
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dclk <= &dff;
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end
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end
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endmodule
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module SegmentController (
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input clk,
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input rst_n,
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input [15:0] signal,
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output [6:0] seg,
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output [3:0] seg_an
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);
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wire dclk;
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wire [3:0] seg_en;
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reg [1:0] cnt;
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reg [6:0] seg_inv;
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reg [3:0] digit;
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ClockDivider #(.N(16)) display(clk, rst_n, dclk);
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always @(posedge clk) begin
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if (!rst_n) begin
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cnt <= 4'd0;
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end else if (dclk) begin
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cnt <= cnt + 1'b1;
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end else begin
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cnt <= cnt;
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end
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end
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always @(*) begin
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case (cnt)
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2'd0: digit = signal[3:0];
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2'd1: digit = signal[7:4];
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2'd2: digit = signal[11:8];
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2'd3: digit = signal[15:12];
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default: digit = 4'd0;
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endcase
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end
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always @(*) begin
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case (digit)
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4'h0: seg_inv = 7'b0111111;
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4'h1: seg_inv = 7'b0000110;
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4'h2: seg_inv = 7'b1011011;
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4'h3: seg_inv = 7'b1001111;
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4'h4: seg_inv = 7'b1100110;
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4'h5: seg_inv = 7'b1101101;
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4'h6: seg_inv = 7'b1111101;
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4'h7: seg_inv = 7'b0000111;
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4'h8: seg_inv = 7'b1111111;
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4'h9: seg_inv = 7'b1101111;
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4'ha: seg_inv = 7'b1110111;
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4'hb: seg_inv = 7'b1111100;
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4'hc: seg_inv = 7'b0111001;
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4'hd: seg_inv = 7'b1011110;
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4'he: seg_inv = 7'b1111001;
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4'hf: seg_inv = 7'b1110001;
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default: seg_inv = 7'b0000000;
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endcase
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end
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assign seg = ~seg_inv;
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assign seg_en = {(signal[15:8] == 8'hE0 ? 2'b11 : 2'b00), 2'b11};
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assign seg_an = ~(seg_en & (4'b1 << cnt));
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endmodule
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