55 lines
1.2 KiB
Verilog
Executable File
55 lines
1.2 KiB
Verilog
Executable File
module SampleDisplay(
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output wire [6:0] display,
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output wire [3:0] digit,
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inout wire PS2_DATA,
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inout wire PS2_CLK,
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input wire rst,
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input wire clk
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);
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wire reset;
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reg [7:0] scan_code, nxt_scan_code;
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wire [511:0] key_down;
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wire [8:0] last_change;
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wire been_ready;
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OnePulse one_pulse(
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.signal_single_pulse(reset),
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.signal(rst),
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.clock(clk)
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);
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SegmentController controller (
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.clk(clk),
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.rst_n(!reset),
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.signal({(last_change[8] ? 8'hE0 : 8'd0), scan_code}),
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.seg(display),
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.seg_an(digit)
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);
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KeyboardDecoder key_de (
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.key_down(key_down),
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.last_change(last_change),
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.key_valid(been_ready),
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.PS2_DATA(PS2_DATA),
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.PS2_CLK(PS2_CLK),
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.rst(reset),
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.clk(clk)
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);
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always @ (posedge clk, posedge reset) begin
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if (reset) begin
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scan_code <= 16'd0;
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end else begin
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scan_code <= nxt_scan_code;
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end
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end
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always @ (*) begin
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if (been_ready && key_down[last_change] == 1'b1) nxt_scan_code = last_change[7:0];
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else nxt_scan_code = scan_code;
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end
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endmodule
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