2021-11-28 22:30:44 +08:00

55 lines
1.2 KiB
Verilog
Executable File

module SampleDisplay(
output wire [6:0] display,
output wire [3:0] digit,
inout wire PS2_DATA,
inout wire PS2_CLK,
input wire rst,
input wire clk
);
wire reset;
reg [7:0] scan_code, nxt_scan_code;
wire [511:0] key_down;
wire [8:0] last_change;
wire been_ready;
OnePulse one_pulse(
.signal_single_pulse(reset),
.signal(rst),
.clock(clk)
);
SegmentController controller (
.clk(clk),
.rst_n(!reset),
.signal({(last_change[8] ? 8'hE0 : 8'd0), scan_code}),
.seg(display),
.seg_an(digit)
);
KeyboardDecoder key_de (
.key_down(key_down),
.last_change(last_change),
.key_valid(been_ready),
.PS2_DATA(PS2_DATA),
.PS2_CLK(PS2_CLK),
.rst(reset),
.clk(clk)
);
always @ (posedge clk, posedge reset) begin
if (reset) begin
scan_code <= 16'd0;
end else begin
scan_code <= nxt_scan_code;
end
end
always @ (*) begin
if (been_ready && key_down[last_change] == 1'b1) nxt_scan_code = last_change[7:0];
else nxt_scan_code = scan_code;
end
endmodule