18 lines
377 B
Verilog
Executable File
18 lines
377 B
Verilog
Executable File
module OnePulse (
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output reg signal_single_pulse,
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input wire signal,
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input wire clock
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);
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reg signal_delay;
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always @(posedge clock) begin
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if (signal == 1'b1 & signal_delay == 1'b0)
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signal_single_pulse <= 1'b1;
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else
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signal_single_pulse <= 1'b0;
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signal_delay <= signal;
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end
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endmodule
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