136 lines
3.9 KiB
Verilog
Executable File
136 lines
3.9 KiB
Verilog
Executable File
module KeyboardDecoder(
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output reg [511:0] key_down,
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output wire [8:0] last_change,
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output reg key_valid,
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inout wire PS2_DATA,
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inout wire PS2_CLK,
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input wire rst,
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input wire clk
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);
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parameter [1:0] INIT = 2'b00;
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parameter [1:0] WAIT_FOR_SIGNAL = 2'b01;
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parameter [1:0] GET_SIGNAL_DOWN = 2'b10;
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parameter [1:0] WAIT_RELEASE = 2'b11;
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parameter [7:0] IS_INIT = 8'hAA;
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parameter [7:0] IS_EXTEND = 8'hE0;
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parameter [7:0] IS_BREAK = 8'hF0;
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reg [9:0] key, next_key; // key = {been_extend, been_break, key_in}
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reg [1:0] state, next_state;
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reg been_ready, been_extend, been_break;
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reg next_been_ready, next_been_extend, next_been_break;
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wire [7:0] key_in;
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wire is_extend;
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wire is_break;
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wire valid;
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wire err;
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wire [511:0] key_decode = 1 << last_change;
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assign last_change = {key[9], key[7:0]};
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KeyboardCtrl_0 inst (
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.key_in(key_in),
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.is_extend(is_extend),
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.is_break(is_break),
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.valid(valid),
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.err(err),
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.PS2_DATA(PS2_DATA),
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.PS2_CLK(PS2_CLK),
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.rst(rst),
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.clk(clk)
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);
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OnePulse op (
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.signal_single_pulse(pulse_been_ready),
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.signal(been_ready),
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.clock(clk)
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);
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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state <= INIT;
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been_ready <= 1'b0;
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been_extend <= 1'b0;
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been_break <= 1'b0;
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key <= 10'b0_0_0000_0000;
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end else begin
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state <= next_state;
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been_ready <= next_been_ready;
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been_extend <= next_been_extend;
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been_break <= next_been_break;
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key <= next_key;
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end
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end
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always @ (*) begin
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case (state)
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INIT: next_state = (key_in == IS_INIT) ? WAIT_FOR_SIGNAL : INIT;
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WAIT_FOR_SIGNAL: next_state = (valid == 1'b0) ? WAIT_FOR_SIGNAL : GET_SIGNAL_DOWN;
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GET_SIGNAL_DOWN: next_state = WAIT_RELEASE;
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WAIT_RELEASE: next_state = (valid == 1'b1) ? WAIT_RELEASE : WAIT_FOR_SIGNAL;
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default: next_state = INIT;
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endcase
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end
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always @ (*) begin
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next_been_ready = been_ready;
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case (state)
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INIT: next_been_ready = (key_in == IS_INIT) ? 1'b0 : next_been_ready;
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WAIT_FOR_SIGNAL: next_been_ready = (valid == 1'b0) ? 1'b0 : next_been_ready;
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GET_SIGNAL_DOWN: next_been_ready = 1'b1;
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WAIT_RELEASE: next_been_ready = next_been_ready;
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default: next_been_ready = 1'b0;
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endcase
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end
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always @ (*) begin
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next_been_extend = (is_extend) ? 1'b1 : been_extend;
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case (state)
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INIT: next_been_extend = (key_in == IS_INIT) ? 1'b0 : next_been_extend;
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WAIT_FOR_SIGNAL: next_been_extend = next_been_extend;
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GET_SIGNAL_DOWN: next_been_extend = next_been_extend;
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WAIT_RELEASE: next_been_extend = (valid == 1'b1) ? next_been_extend : 1'b0;
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default: next_been_extend = 1'b0;
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endcase
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end
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always @ (*) begin
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next_been_break = (is_break) ? 1'b1 : been_break;
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case (state)
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INIT: next_been_break = (key_in == IS_INIT) ? 1'b0 : next_been_break;
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WAIT_FOR_SIGNAL: next_been_break = next_been_break;
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GET_SIGNAL_DOWN: next_been_break = next_been_break;
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WAIT_RELEASE: next_been_break = (valid == 1'b1) ? next_been_break : 1'b0;
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default: next_been_break = 1'b0;
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endcase
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end
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always @ (*) begin
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next_key = key;
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case (state)
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INIT: next_key = (key_in == IS_INIT) ? 10'b0_0_0000_0000 : next_key;
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WAIT_FOR_SIGNAL: next_key = next_key;
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GET_SIGNAL_DOWN: next_key = {been_extend, been_break, key_in};
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WAIT_RELEASE: next_key = next_key;
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default: next_key = 10'b0_0_0000_0000;
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endcase
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end
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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key_valid <= 1'b0;
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key_down <= 511'b0;
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end else if (key_decode[last_change] && pulse_been_ready) begin
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key_valid <= 1'b1;
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if (key[8] == 0) begin
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key_down <= key_down | key_decode;
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end else begin
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key_down <= key_down & (~key_decode);
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end
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end else begin
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key_valid <= 1'b0;
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key_down <= key_down;
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end
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end
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endmodule
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