67 lines
1.7 KiB
Verilog
Executable File
67 lines
1.7 KiB
Verilog
Executable File
module SevenSegment(
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output reg [6:0] display,
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output reg [3:0] digit,
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input wire [15:0] nums,
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input wire rst,
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input wire clk
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);
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reg [15:0] clk_divider;
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reg [3:0] display_num;
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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clk_divider <= 15'b0;
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end else begin
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clk_divider <= clk_divider + 15'b1;
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end
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end
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always @ (posedge clk_divider[15], posedge rst) begin
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if (rst) begin
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display_num <= 4'b0000;
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digit <= 4'b1111;
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end else begin
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case (digit)
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4'b1110 : begin
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display_num <= nums[7:4];
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digit <= 4'b1101;
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end
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4'b1101 : begin
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display_num <= nums[11:8];
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digit <= 4'b1011;
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end
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4'b1011 : begin
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display_num <= nums[15:12];
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digit <= 4'b0111;
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end
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4'b0111 : begin
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display_num <= nums[3:0];
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digit <= 4'b1110;
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end
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default : begin
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display_num <= nums[3:0];
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digit <= 4'b1110;
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end
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endcase
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end
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end
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always @ (*) begin
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case (display_num)
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0 : display = 7'b1000000; //0000
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1 : display = 7'b1111001; //0001
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2 : display = 7'b0100100; //0010
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3 : display = 7'b0110000; //0011
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4 : display = 7'b0011001; //0100
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5 : display = 7'b0010010; //0101
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6 : display = 7'b0000010; //0110
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7 : display = 7'b1111000; //0111
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8 : display = 7'b0000000; //1000
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9 : display = 7'b0010000; //1001
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default : display = 7'b1111111;
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endcase
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end
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endmodule
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