258 lines
12 KiB
XML
Executable File
258 lines
12 KiB
XML
Executable File
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>KeyboardCtrl</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>KeyboardCtrl</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>c8a2a715</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>KeyboardCtrl</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>c8a2a715</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>ce6920f7</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>key_in</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>is_extend</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>is_break</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>valid</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>err</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>PS2_DATA</spirit:name>
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<spirit:wire>
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<spirit:direction>inout</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>PS2_CLK</spirit:name>
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<spirit:wire>
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<spirit:direction>inout</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>rst</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>clk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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<spirit:modelParameters>
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<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
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<spirit:name>SYSCLK_FREQUENCY_HZ</spirit:name>
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<spirit:displayName>Sysclk Frequency Hz</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SYSCLK_FREQUENCY_HZ">100000000</spirit:value>
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</spirit:modelParameter>
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</spirit:modelParameters>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>src/Ps2Interface.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>src/KeyboardCtrl.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_36baf34c</spirit:userFileType>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>src/Ps2Interface.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:file>
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<spirit:name>src/KeyboardCtrl.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/KeyboardCtrl_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_407cc9d0</spirit:userFileType>
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<spirit:description>KeyboardCtrl_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>SYSCLK_FREQUENCY_HZ</spirit:name>
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<spirit:displayName>Sysclk Frequency Hz</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SYSCLK_FREQUENCY_HZ">100000000</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">KeyboardCtrl_v1_0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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<xilinx:displayName>KeyboardCtrl_v1_0</xilinx:displayName>
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<xilinx:coreRevision>2</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2015-05-31T12:51:28Z</xilinx:coreCreationDateTime>
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<xilinx:tags>
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<xilinx:tag xilinx:name="xilinx.com:ip:KeyboardCtrl:1.0_ARCHIVE_LOCATION">C:/Users/bill/Desktop/zedboard/basys3/Basys3_master/Library/Interface/Keyboard-Controller/keyboard_cntr_1.0</xilinx:tag>
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<xilinx:tag xilinx:name="xilinx.com:user:KeyboardCtrl:1.0_ARCHIVE_LOCATION">C:/Users/bill/Desktop/zedboard/basys3/Basys3_master/Library/Interface/Keyboard-Controller/keyboard_cntr_1.0</xilinx:tag>
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</xilinx:tags>
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