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Fix if-else problem

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Samuel Huang 2021-11-26 17:45:57 +08:00
parent a22ff94e72
commit 55edf9006f
1 changed files with 58 additions and 49 deletions
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103
Keyboard Sample Code/KeyboardDecoder.v
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@ -17,9 +17,10 @@ module KeyboardDecoder(
parameter [7:0] IS_EXTEND = 8'hE0;
parameter [7:0] IS_BREAK = 8'hF0;
reg [9:0] key; // key = {been_extend, been_break, key_in}
reg [1:0] state;
reg [9:0] key, next_key; // key = {been_extend, been_break, key_in}
reg [1:0] state, next_state;
reg been_ready, been_extend, been_break;
reg next_been_ready, next_been_extend, next_been_break;
wire [7:0] key_in;
wire is_extend;
@ -56,54 +57,62 @@ module KeyboardDecoder(
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end else begin
state <= state;
been_ready <= been_ready;
been_extend <= (is_extend) ? 1'b1 : been_extend;
been_break <= (is_break ) ? 1'b1 : been_break;
key <= key;
state <= next_state;
been_ready <= next_been_ready;
been_extend <= next_been_extend;
been_break <= next_been_break;
key <= next_key;
end
end
always @ (*) begin
case (state)
INIT : begin
if (key_in == IS_INIT) begin
state <= WAIT_FOR_SIGNAL;
been_ready <= 1'b0;
been_extend <= 1'b0;
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end else begin
state <= INIT;
end
end
WAIT_FOR_SIGNAL : begin
if (valid == 0) begin
state <= WAIT_FOR_SIGNAL;
been_ready <= 1'b0;
end else begin
state <= GET_SIGNAL_DOWN;
end
end
GET_SIGNAL_DOWN : begin
state <= WAIT_RELEASE;
key <= {been_extend, been_break, key_in};
been_ready <= 1'b1;
end
WAIT_RELEASE : begin
if (valid == 1) begin
state <= WAIT_RELEASE;
end else begin
state <= WAIT_FOR_SIGNAL;
been_extend <= 1'b0;
been_break <= 1'b0;
end
end
default : begin
state <= INIT;
been_ready <= 1'b0;
been_extend <= 1'b0;
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end
INIT: next_state = (key_in == IS_INIT) ? WAIT_FOR_SIGNAL : INIT;
WAIT_FOR_SIGNAL: next_state = (valid == 1'b0) ? WAIT_FOR_SIGNAL : GET_SIGNAL_DOWN;
GET_SIGNAL_DOWN: next_state = WAIT_RELEASE;
WAIT_RELEASE: next_state = (valid == 1'b1) ? WAIT_RELEASE : WAIT_FOR_SIGNAL;
default: next_state = INIT;
endcase
end
always @ (*) begin
next_been_ready = been_ready;
case (state)
INIT: next_been_ready = (key_in == IS_INIT) ? 1'b0 : next_been_ready;
WAIT_FOR_SIGNAL: next_been_ready = (valid == 1'b0) ? 1'b0 : next_been_ready;
GET_SIGNAL_DOWN: next_been_ready = 1'b1;
WAIT_RELEASE: next_been_ready = next_been_ready;
default: next_been_ready = 1'b0;
endcase
end
always @ (*) begin
next_been_extend = (is_extend) ? 1'b1 : been_extend;
case (state)
INIT: next_been_extend = (key_in == IS_INIT) ? 1'b0 : next_been_extend;
WAIT_FOR_SIGNAL: next_been_extend = next_been_extend;
GET_SIGNAL_DOWN: next_been_extend = next_been_extend;
WAIT_RELEASE: next_been_extend = (valid == 1'b1) ? next_been_extend : 1'b0;
default: next_been_extend = 1'b0;
endcase
end
always @ (*) begin
next_been_break = (is_break) ? 1'b1 : been_break;
case (state)
INIT: next_been_break = (key_in == IS_INIT) ? 1'b0 : next_been_break;
WAIT_FOR_SIGNAL: next_been_break = next_been_break;
GET_SIGNAL_DOWN: next_been_break = next_been_break;
WAIT_RELEASE: next_been_break = (valid == 1'b1) ? next_been_break : 1'b0;
default: next_been_break = 1'b0;
endcase
end
always @ (*) begin
next_key = key;
case (state)
INIT: next_key = (key_in == IS_INIT) ? 10'b0_0_0000_0000 : next_key;
WAIT_FOR_SIGNAL: next_key = next_key;
GET_SIGNAL_DOWN: next_key = {been_extend, been_break, key_in};
WAIT_RELEASE: next_key = next_key;
default: next_key = 10'b0_0_0000_0000;
endcase
end
always @ (posedge clk, posedge rst) begin