fix indent

This commit is contained in:
Samuel Huang 2021-11-26 18:25:53 +08:00
parent 7c579b6323
commit 8e80429bc1
2 changed files with 17 additions and 18 deletions

View File

@ -8,10 +8,9 @@ module OnePulse (
always @(posedge clock) begin
if (signal == 1'b1 & signal_delay == 1'b0)
signal_single_pulse <= 1'b1;
signal_single_pulse <= 1'b1;
else
signal_single_pulse <= 1'b0;
signal_single_pulse <= 1'b0;
signal_delay <= signal;
end
endmodule

View File

@ -24,25 +24,25 @@ module SevenSegment(
end else if (clk_divider == {16{1'b1}}) begin
case (digit)
4'b1110 : begin
display_num <= nums[7:4];
digit <= 4'b1101;
end
display_num <= nums[7:4];
digit <= 4'b1101;
end
4'b1101 : begin
display_num <= nums[11:8];
digit <= 4'b1011;
end
display_num <= nums[11:8];
digit <= 4'b1011;
end
4'b1011 : begin
display_num <= nums[15:12];
digit <= 4'b0111;
end
display_num <= nums[15:12];
digit <= 4'b0111;
end
4'b0111 : begin
display_num <= nums[3:0];
digit <= 4'b1110;
end
display_num <= nums[3:0];
digit <= 4'b1110;
end
default : begin
display_num <= nums[3:0];
digit <= 4'b1110;
end
display_num <= nums[3:0];
digit <= 4'b1110;
end
endcase
end else begin
display_num <= display_num;