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fix indent

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This commit is contained in:
Samuel Huang 2021-11-26 18:25:53 +08:00
parent 7c579b6323
commit 8e80429bc1
2 changed files with 17 additions and 18 deletions
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5
Keyboard Sample Code/OnePulse.v
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@ -8,10 +8,9 @@ module OnePulse (
always @(posedge clock) begin always @(posedge clock) begin
if (signal == 1'b1 & signal_delay == 1'b0) if (signal == 1'b1 & signal_delay == 1'b0)
signal_single_pulse <= 1'b1; signal_single_pulse <= 1'b1;
else else
signal_single_pulse <= 1'b0; signal_single_pulse <= 1'b0;
signal_delay <= signal; signal_delay <= signal;
end end
endmodule endmodule

30
Keyboard Sample Code/SevenSegment.v
View File

@ -24,25 +24,25 @@ module SevenSegment(
end else if (clk_divider == {16{1'b1}}) begin end else if (clk_divider == {16{1'b1}}) begin
case (digit) case (digit)
4'b1110 : begin 4'b1110 : begin
display_num <= nums[7:4]; display_num <= nums[7:4];
digit <= 4'b1101; digit <= 4'b1101;
end end
4'b1101 : begin 4'b1101 : begin
display_num <= nums[11:8]; display_num <= nums[11:8];
digit <= 4'b1011; digit <= 4'b1011;
end end
4'b1011 : begin 4'b1011 : begin
display_num <= nums[15:12]; display_num <= nums[15:12];
digit <= 4'b0111; digit <= 4'b0111;
end end
4'b0111 : begin 4'b0111 : begin
display_num <= nums[3:0]; display_num <= nums[3:0];
digit <= 4'b1110; digit <= 4'b1110;
end end
default : begin default : begin
display_num <= nums[3:0]; display_num <= nums[3:0];
digit <= 4'b1110; digit <= 4'b1110;
end end
endcase endcase
end else begin end else begin
display_num <= display_num; display_num <= display_num;