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keyboard-sample
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Samuel Huang
dd4aa79cfd
Change syntax of parameter-parity_table from SystemVerilog to Verilog.
2021-11-26 18:11:04 +08:00
Keyboard Sample Code
Change syntax of parameter-parity_table from SystemVerilog to Verilog.
2021-11-26 18:11:04 +08:00
.DS_Store
Initial commit
2021-11-26 17:16:16 +08:00
Description
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74
KiB
Languages
Verilog
97.5%
Tcl
2.5%