Samuel Huang e8ee999e8f C1) hange syntax of KEYCODE-parameter from SystemVerilog to Verilog. 2) Fix if-else problem

2021-11-26 17:59:29 +08:00

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C1) hange syntax of KEYCODE-parameter from SystemVerilog to Verilog. 2) Fix if-else problem

2021-11-26 17:59:29 +08:00

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Initial commit

2021-11-26 17:16:16 +08:00

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74 KiB

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Verilog 97.5%

Tcl 2.5%