[Feature] show scan code on 7-segment
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Tony Yang
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bd88e52694
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36686d8f1a
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D88388851C28715D
@ -19,8 +19,8 @@ set_property PACKAGE_PIN V5 [get_ports {display[5]}]
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set_property PACKAGE_PIN U7 [get_ports {display[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {display[6]}]
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#set_property PACKAGE_PIN V7 [get_ports dp]
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#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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# set_property PACKAGE_PIN V7 [get_ports dp]
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# set_property IOSTANDARD LVCMOS33 [get_ports dp]
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set_property PACKAGE_PIN U2 [get_ports {digit[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {digit[0]}]
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@ -5,49 +5,27 @@ module SampleDisplay(
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inout wire PS2_CLK,
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input wire rst,
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input wire clk
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);
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);
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wire reset;
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parameter [8:0] LEFT_SHIFT_CODES = 9'b0_0001_0010;
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parameter [8:0] RIGHT_SHIFT_CODES = 9'b0_0101_1001;
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parameter [8:0] KEY_CODES_00 = 9'b0_0100_0101; // 0 => 45
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parameter [8:0] KEY_CODES_01 = 9'b0_0001_0110; // 1 => 16
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parameter [8:0] KEY_CODES_02 = 9'b0_0001_1110; // 2 => 1E
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parameter [8:0] KEY_CODES_03 = 9'b0_0010_0110; // 3 => 26
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parameter [8:0] KEY_CODES_04 = 9'b0_0010_0101; // 4 => 25
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parameter [8:0] KEY_CODES_05 = 9'b0_0010_1110; // 5 => 2E
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parameter [8:0] KEY_CODES_06 = 9'b0_0011_0110; // 6 => 36
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parameter [8:0] KEY_CODES_07 = 9'b0_0011_1101; // 7 => 3D
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parameter [8:0] KEY_CODES_08 = 9'b0_0011_1110; // 8 => 3E
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parameter [8:0] KEY_CODES_09 = 9'b0_0100_0110; // 9 => 46
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reg [7:0] scan_code, nxt_scan_code;
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parameter [8:0] KEY_CODES_10 = 9'b0_0111_0000; // right_0 => 70
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parameter [8:0] KEY_CODES_11 = 9'b0_0110_1001; // right_1 => 69
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parameter [8:0] KEY_CODES_12 = 9'b0_0111_0010; // right_2 => 72
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parameter [8:0] KEY_CODES_13 = 9'b0_0111_1010; // right_3 => 7A
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parameter [8:0] KEY_CODES_14 = 9'b0_0110_1011; // right_4 => 6B
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parameter [8:0] KEY_CODES_15 = 9'b0_0111_0011; // right_5 => 73
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parameter [8:0] KEY_CODES_16 = 9'b0_0111_0100; // right_6 => 74
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parameter [8:0] KEY_CODES_17 = 9'b0_0110_1100; // right_7 => 6C
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parameter [8:0] KEY_CODES_18 = 9'b0_0111_0101; // right_8 => 75
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parameter [8:0] KEY_CODES_19 = 9'b0_0111_1101; // right_9 => 7D
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reg [15:0] nums, next_nums;
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reg [3:0] key_num;
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reg [9:0] last_key;
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wire shift_down;
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wire [511:0] key_down;
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wire [8:0] last_change;
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wire been_ready;
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assign shift_down = (key_down[LEFT_SHIFT_CODES] == 1'b1 || key_down[RIGHT_SHIFT_CODES] == 1'b1) ? 1'b1 : 1'b0;
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OnePulse one_pulse(
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.signal_single_pulse(reset),
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.signal(rst),
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.clock(clk)
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);
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SevenSegment seven_seg (
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.display(display),
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.digit(digit),
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.nums(nums),
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.rst(rst),
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.clk(clk)
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SegmentController controller (
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.clk(clk),
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.rst_n(!reset),
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.signal({(last_change[8] ? 8'hE0 : 8'd0), scan_code}),
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.seg(display),
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.seg_an(digit)
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);
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KeyboardDecoder key_de (
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@ -56,54 +34,21 @@ module SampleDisplay(
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.key_valid(been_ready),
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.PS2_DATA(PS2_DATA),
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.PS2_CLK(PS2_CLK),
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.rst(rst),
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.rst(reset),
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.clk(clk)
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);
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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nums <= 16'b0;
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always @ (posedge clk, posedge reset) begin
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if (reset) begin
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scan_code <= 16'd0;
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end else begin
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nums <= next_nums;
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scan_code <= nxt_scan_code;
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end
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end
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always @ (*) begin
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next_nums = nums;
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if (been_ready && key_down[last_change] == 1'b1) begin
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if (key_num != 4'b1111) begin
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if (shift_down == 1'b1) begin
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next_nums = {key_num, nums[15:4]};
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end else begin
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next_nums = {nums[11:0], key_num};
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end
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end else next_nums = next_nums;
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end else next_nums = next_nums;
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end
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always @ (*) begin
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case (last_change)
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KEY_CODES_00 : key_num = 4'b0000;
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KEY_CODES_01 : key_num = 4'b0001;
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KEY_CODES_02 : key_num = 4'b0010;
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KEY_CODES_03 : key_num = 4'b0011;
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KEY_CODES_04 : key_num = 4'b0100;
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KEY_CODES_05 : key_num = 4'b0101;
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KEY_CODES_06 : key_num = 4'b0110;
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KEY_CODES_07 : key_num = 4'b0111;
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KEY_CODES_08 : key_num = 4'b1000;
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KEY_CODES_09 : key_num = 4'b1001;
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KEY_CODES_10 : key_num = 4'b0000;
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KEY_CODES_11 : key_num = 4'b0001;
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KEY_CODES_12 : key_num = 4'b0010;
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KEY_CODES_13 : key_num = 4'b0011;
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KEY_CODES_14 : key_num = 4'b0100;
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KEY_CODES_15 : key_num = 4'b0101;
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KEY_CODES_16 : key_num = 4'b0110;
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KEY_CODES_17 : key_num = 4'b0111;
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KEY_CODES_18 : key_num = 4'b1000;
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KEY_CODES_19 : key_num = 4'b1001;
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default : key_num = 4'b1111;
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endcase
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if (been_ready && key_down[last_change] == 1'b1) nxt_scan_code = last_change[7:0];
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else nxt_scan_code = scan_code;
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end
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endmodule
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@ -1,69 +1,81 @@
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module SevenSegment(
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output reg [6:0] display,
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output reg [3:0] digit,
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input wire [15:0] nums,
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input wire rst,
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input wire clk
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);
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reg [15:0] clk_divider;
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reg [3:0] display_num;
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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clk_divider <= 16'b0;
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module ClockDivider #(
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parameter N = 20
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) (
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input clk,
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input rst_n,
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output reg dclk
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);
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reg [N-1:0] dff;
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always @(posedge clk) begin
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if (!rst_n) begin
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dff <= {N{1'b0}};
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end else begin
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clk_divider <= clk_divider + 16'b1;
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dff <= dff + 1'b1;
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dclk <= &dff;
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end
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end
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endmodule
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module SegmentController (
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input clk,
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input rst_n,
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input [15:0] signal,
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output [6:0] seg,
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output [3:0] seg_an
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);
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wire dclk;
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wire [3:0] seg_en;
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reg [1:0] cnt;
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reg [6:0] seg_inv;
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reg [3:0] digit;
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ClockDivider #(.N(16)) display(clk, rst_n, dclk);
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always @(posedge clk) begin
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if (!rst_n) begin
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cnt <= 4'd0;
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end else if (dclk) begin
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cnt <= cnt + 1'b1;
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end else begin
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cnt <= cnt;
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end
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end
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always @ (posedge clk, posedge rst) begin
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if (rst) begin
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display_num <= 4'b0000;
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digit <= 4'b1111;
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end else if (clk_divider == {16{1'b1}}) begin
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case (digit)
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4'b1110 : begin
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display_num <= nums[7:4];
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digit <= 4'b1101;
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end
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4'b1101 : begin
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display_num <= nums[11:8];
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digit <= 4'b1011;
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end
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4'b1011 : begin
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display_num <= nums[15:12];
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digit <= 4'b0111;
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end
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4'b0111 : begin
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display_num <= nums[3:0];
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digit <= 4'b1110;
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end
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default : begin
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display_num <= nums[3:0];
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digit <= 4'b1110;
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end
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endcase
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end else begin
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display_num <= display_num;
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digit <= digit;
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end
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end
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always @ (*) begin
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case (display_num)
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0 : display = 7'b1000000; //0000
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1 : display = 7'b1111001; //0001
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2 : display = 7'b0100100; //0010
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3 : display = 7'b0110000; //0011
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4 : display = 7'b0011001; //0100
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5 : display = 7'b0010010; //0101
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6 : display = 7'b0000010; //0110
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7 : display = 7'b1111000; //0111
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8 : display = 7'b0000000; //1000
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9 : display = 7'b0010000; //1001
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default : display = 7'b1111111;
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always @(*) begin
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case (cnt)
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2'd0: digit = signal[3:0];
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2'd1: digit = signal[7:4];
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2'd2: digit = signal[11:8];
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2'd3: digit = signal[15:12];
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default: digit = 4'd0;
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endcase
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end
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always @(*) begin
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case (digit)
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4'h0: seg_inv = 7'b0111111;
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4'h1: seg_inv = 7'b0000110;
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4'h2: seg_inv = 7'b1011011;
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4'h3: seg_inv = 7'b1001111;
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4'h4: seg_inv = 7'b1100110;
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4'h5: seg_inv = 7'b1101101;
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4'h6: seg_inv = 7'b1111101;
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4'h7: seg_inv = 7'b0000111;
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4'h8: seg_inv = 7'b1111111;
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4'h9: seg_inv = 7'b1101111;
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4'ha: seg_inv = 7'b1110111;
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4'hb: seg_inv = 7'b1111100;
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4'hc: seg_inv = 7'b0111001;
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4'hd: seg_inv = 7'b1011110;
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4'he: seg_inv = 7'b1111001;
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4'hf: seg_inv = 7'b1110001;
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default: seg_inv = 7'b0000000;
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endcase
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end
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assign seg = ~seg_inv;
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assign seg_en = {(signal[15:8] == 8'hE0 ? 2'b11 : 2'b00), 2'b11};
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assign seg_an = ~(seg_en & (4'b1 << cnt));
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endmodule
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