Samuel Huang
|
3e71036abc
|
Convert tabs to spaces
|
2021-11-26 18:22:42 +08:00 |
|
Samuel Huang
|
c2c8ec302e
|
Fix dclk as DFF trigger clock
|
2021-11-26 18:16:05 +08:00 |
|
Samuel Huang
|
dd4aa79cfd
|
Change syntax of parameter-parity_table from SystemVerilog to Verilog.
|
2021-11-26 18:11:04 +08:00 |
|
Samuel Huang
|
e8ee999e8f
|
C1) hange syntax of KEYCODE-parameter from SystemVerilog to Verilog. 2) Fix if-else problem
|
2021-11-26 17:59:29 +08:00 |
|
Samuel Huang
|
55edf9006f
|
Fix if-else problem
|
2021-11-26 17:45:57 +08:00 |
|
Samuel Huang
|
a22ff94e72
|
Initial commit
|
2021-11-26 17:16:16 +08:00 |
|