Samuel Huang
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bd88e52694
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Optimize if-else
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2021-11-27 11:53:35 +08:00 |
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Samuel Huang
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56f40b1a75
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Fix KeyboardCtrl.v: if-else problem and optimize nested if statements
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2021-11-27 11:47:14 +08:00 |
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Samuel Huang
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8e80429bc1
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fix indent
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2021-11-26 18:25:53 +08:00 |
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Samuel Huang
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7c579b6323
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Merge branch 'master' of ssh://git.enmingw32.dev:2287/Verilog/keyboard-sample
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2021-11-26 18:22:47 +08:00 |
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Samuel Huang
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3e71036abc
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Convert tabs to spaces
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2021-11-26 18:22:42 +08:00 |
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Samuel Huang
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2a898ba747
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delete .DS_Store
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2021-11-26 18:20:54 +08:00 |
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Samuel Huang
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c2c8ec302e
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Fix dclk as DFF trigger clock
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2021-11-26 18:16:05 +08:00 |
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Samuel Huang
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dd4aa79cfd
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Change syntax of parameter-parity_table from SystemVerilog to Verilog.
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2021-11-26 18:11:04 +08:00 |
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Samuel Huang
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e8ee999e8f
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C1) hange syntax of KEYCODE-parameter from SystemVerilog to Verilog. 2) Fix if-else problem
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2021-11-26 17:59:29 +08:00 |
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Samuel Huang
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55edf9006f
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Fix if-else problem
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2021-11-26 17:45:57 +08:00 |
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Samuel Huang
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a22ff94e72
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Initial commit
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2021-11-26 17:16:16 +08:00 |
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